Data transmission



Aug. 13, 1963 H. A. HENNING DATA TRANSMISSION 4 Sheets-Sheet 2 ATTORNEY Aug.13,1963 y H.A.HENN|NG .3,100,890

DATA TRANSMISSION Filed oct. 11, 1960 4 sneetshem 3 .SQUARE/P l :muso/DA1. GENERATOR /N VEA/TOR H A. HE NN/NG @Y QM-Wy@ ATTORNEY Aug. 13, 1963 H A. HENNING DATA TRANSMISSION' Filed oct.` 11, 1960 4 Sheets-Sheet 4 E E S S S /NVE/vrop H. ,4. HE/V/V/NG BV l ATTORNEY S E s E,

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United States at 3,100,890 DATA TRANSMISSIQN Harley A. Henning, Short Hills, NJ., assignor to Bell `Telephone Laboratories, Incorporated, New`York,

N.Y., a corporation of New York Filed ct.`11, 1960, Ser. No. 61,862 Claims. (Cl. 3404-345) This inventionrelates inigeneral to data communications systems and more specifically to phase-shift transmitters for such systems.

"In recent years considerable' interesthas been arousedv in the possibilitiesof'putting the considerable investment 'in switched voice telephone circuits to use for the transmission of digital data between telephone subscribers. Such services in the past have generally beenk provided onprivate line facilities, theV transmission characteristics of which can be adjusted for optimumdata transmission requirements. vThe increased'use of computers andautomatic `dataprocessing systems has so Aaugmented the demand for data services thatv it is rapidly becoming impracticable to furnish suicient' privatewire facilities.

Besides, the customer is often unwilling toy pay the increased' cost of private'line circuits.

The switched telephone network has been built up over the years primarilyl to meet the requirements of voiceV communications. The characteristics engineered into the system, While usable for datal transmission, are not optimal for this service. The bandwidth of a `voice channel is narrower than might be desired, and is not i generally usable below vaboutO cycles per second. This characteristic limits transmission speeds and virtually precludes the direct transmission of data which has a directcurrent component. The circuit net loss is such as to reduce the effective signal-to-noise ratio Vand thereby [to the on-oif data bits to carrier frequencies centeredy in the voice band.. Phase modulation techniques have Abeen found particularly effective in Vovercoming the noise problems` encountered inusing voicetelephone circuits for transmitting data. l u

'Most data transmission systems arehsynchronous, i.e., a common timing source or clock links transmitter and receiver in ord-er to insure accurate interpretation of the transmittedmessage. 'Data messages are `generally encoded into binary digits, or bits, and each digit or bit is assigned to an equall length time interval for transmission purposes. The problem at the receiver is to recognize the occurrence of these time intervals and to sample the interval at the correct instant .to `determine the'nature of the bit transmitted therein. It has been found in a v phase modulation systemthat two successive bits can be transmitted as a single shift in phase. ySince there are only four possible bitpair combinations, only four discrete phases are` needed to transmit all possible digital messages.V Furthermore, these discrete phases need not be absolute phases,` but may be relative phases. Each successive phase shift need only be made with'respect to the previous phase transmitted.

Where a relative phase shift system isadopted, a stored reference vreceiving system is generally employed. In such a receiving system leach received phase isA stored for one bit interval and compared with the next succeeding phase to determine-what phase shift has occurred.

Patented Aug. 1 3, 1963 A storedV reference system phasedlocal carrier generator at the receiver.

Although the `'four-phase data transmission system outlined above is generally satisfactory in the case of random signals, in the case of certain repeated signals of the same coding no phase shifts are generated and the transmitted signal degenerates into pure carrier. Synchronism between transmitter and receiver is lost. It has, therefore, been suggested to superimpose on the phase shifts resulting from the change in coding from interval to interval in the four-phase system an arbitrary xed phase shift whether the coding changes or not. This fixed phase shift may conveniently be 45 degrees. -The four-phase syst-em is then transformed into an eight-phase system and a minimum phase advance or retardation of 45 degrees in `phase of the carrier frequency'is secured even for repeated signals. Synchronism between -tran'smittel-fand receiver is preserved at all times fand no additional channelspace is required to transmit timing information. f

Although eight-phase data ltransmission systems are known to the prior art, the means for realizing a practical system have., been unnecessarily complex andcumbersome. 'It is, therefore, a general object'of this. invention to' simplify the realization of an eight-phase"v data transmission system. It is a further object of this invencoded as one of eight relative phases on a single frequency Y tion to generate the phase-shifted carrier wave solely by digital means. It is analternative object to determine the necessary carrier phase by digital means but to control thereby the phase of a sinusoidal carrier wave.

According to this invention a serialv binary data signal Iafter conversion into two-bit parallel or dibit form is encarrier wave. A register and control circuit, here called a vector keyer from its function of ldetermining-the direction andarnount of rotation of the carrier frequency phase vector, stores information on 4the phase of the carrier frequency vector then being transmitted,` computes the phase rotation next to be imparted tothe carrier frequency according to the dibit combination to be'transmitted and provides control signals to a carrier modulator. Taking advantage of the facts that all eight phase vectors can be representedby4 sums of 45, 90 and 180 degrees taken one, two and three at fa' time and that these three phases are in the ratio of 1:2:4, the eight possiblel phases are stored and manipulated inthe Vector keyer vas aimee-digit binary number. `The most significant digit represents l80degrees; the next most significant, 90 degreesgand the 'least significant, 45 degrees. The vector keyer `is therefore a three-stage counting register with its basicv counting rate controlled by a clock generator. For

each clockr pulse the keyer samples'. the `dibit signal cornbinationand adds 'or-.subtracts an appropriate amount according lto a predetermined code such that a minimum count of one' (equivalent to a phasechange of 45 Vdegrees) is added' to or subtracted fromthe ycontents of its register. This insures that a phase shift is imparted to the carrier'frequencyhin each Fdibit interval. The outputs ofthe three stages of the vector keyer serve as control ysignals :applied to a carrier wave modulator.k

According .to Ione embodiment of this invention, the

digital outputs of the vector keyer lare used to key synchronized square waves having frequencies of four, two and one times vthe carrier Viirequency in a modulator oircuit to an output bistable circuit lto produce a rectangular and 'a phase shift which changes in each dibit interval; The synchronized square Waves are Vderived from a stable frequency source eight times 'the frequency of the carrierl wave. A -smoothoutput wave is obtained by passing the output of the bistable circuit through a. low-pass filter.

In another embodiment of vthe invention the several obviates having an accurately` outputs 'of ythe vector keyer are applied to separate reversing modulators.

quadrature components.v The direct component is modulated Withthe ISO-degree output ofthe vector keyer toquadrature components are added together and the resultant is shifted 45 degrees or not according to the 45- degree output `of the vector keyer.

.The output signals from each of these embodiments aire substantially identical and represent the serial data message as rela-tive phases of the single-frequency carrier wave.

An important feature of this invention is thlat synchroninin'g informationis inherent in the transmitted signal because of the fact-that a minimum phase shift is always provided between data combinations. No auxiliary timing sources are, therefore, requiredat'the receiving end ofa transmission line onV whichfthese signals are impressed.

' A more complete understanding and appreciation of Y this invention can be obtained lfrom the following detailed description together with the drawings in which:

FIG. 1 is `a block diagram of an all-digital phase-pulse modulator according to this invention; JFIG.'2 is a block` diagram of another vembodiment of this invention lwhich employs a sinusoidal carrier wave generator; g l FIG. 3 is a b lock diagram showing in more detail a invention; y FIG. 4.is a detailedrblock diagram of la vector keyer useful in the practicefof this invention; FIG. 5 is a detailed block diagram of la digital carrierivave generator according to this invention;` and UFIMG.` 6\is a pulse diagram useful in explaining the operationof theem'bodiments of thisinvention. In transmitting a binarysignal, twov signal conditions are required,namely: the presence of the specific signal and" its absence. The presenceof the specific signal is senial-to-parallel converter useful` inthe practice of this i Lconventionally designated as l and its absence as 0u The fl` signal may be represented as the presence of a vol-tage' and the \0\ by its absence. As an alternative the fl may be represented by ground and its absence by la negative voltage. This latterconvention is assumed in the following description. i n In a phase-pulse system, that is, la system in which pulses yare encoded as shifts in phase of a single-frequeney'carrier Wave, the binary digits or bits may be encoded as absolute phases such as O` and 18() degrees or as relative phase shifts where each preceding signal serves as a reference for the succeeding signal. lIn using the relative phase shift system, it has been found that more infomation can be transmitted ina given time interval by adopting a, quadrature phase shiftsystem.k By this means [seria-l datalcan be encoded into signal pairs, which may be denominated dibits for brevity. ln the alternative two otherwise independent channels of digital information can be paired bit by bit and transmitted on a single channel. In the serial case transmission occurs at hal-f the serial rate/.11n the dual channel case transmission is at the source rate. There` are clearly four paired signal codes, namely: 0U, 01, l() land 11. These codes may be assigned .any particular phase shift of a quadrature set. ln the 'shifts are 'all'multiples of 45 degrees, it isreadily seen that a random signal sequence will result in the carrier phase vector occupying any of eight absolute phase v positions Which :are multiples of 45 degrees. Furthermore,

, each successive code combination will place Ithe phase vector alternately on one ofI two quadrature phase axis In this embodiment a sinusoidal carrier wave generator has its output split into direct and 4 sets. One quadrature phase axis includes the absolute phases 0, 90, 18() and 270 degrees. Therother quadra- V ture phase axis includes the absolute phases 45, 135, 225

e 1li, a serial-to-parallel converter 11, a vector keyer 1,2, a Y

and 315 degrees. It is, therefore, evident that any'repeated signal codes will generate a minimum 45-degree phase shift. v

Although the use of the invariant 45adegree phase shift between -dibit intervals insures a phase shift between starts of successive dibit intervals, nevertheless Vsmooth transitions may occur with certainsignal combinations f' unless an integral number of quarter cycles of carrier ore present in each dibit timing interval. For the purposes of this description lthe dibit rate is assumed Ito be 1000 and the carrier frequency, 1500fcycles per second, thus yielding one and one-half cycles of 'carrier for each dibit. This carrier frequency is near .the center of the voice band, and is readily transmitted through the switched telephone network. It is to be understood that other data rates and carrier frequencies may be used, if desired.

Referring now* to IFIG. l, one sees an all-digital phase modulation system for the transmission of binary digital data in two-bit parallel form. The system comprises to the lef-t of dash-'dotvertical line A--A a serial data source clock generator 16 and a delay network 17. To the right ,of the line A-A the system of one embodiment further comprisesV amodulator 13, a square-wave generator 15,

second. The square-wave generator 15 may be of simi-f lar form, but is preferably crystal-controlled to provide a 12l ilocycle per second output square wave. For precision control of theI yclock generator la :lockingeconnection indicated by line I11501 may be provided betweenV the carrier generator 15 and the clock generator 116 in any well-known manner. The clock generator provides a direct output to the vector-keyer 12 land a delayed output through delay network l17 to datasource 10 and converter 11 by way of lines k19and 18, respectively. The delay need only be a small traction, say l0 percent, of the dibit interval in order to insure that the converter outputs lare present when thevector'lceyer samples the output thereof.

The serial data source may bea tape orcard reader or similar device ready to furnish data at twice the ldibit ra-te.

The data source is signaled over line :19 when the system Y is prepared to accept data Iandvthis -signal controls'th rate of removal of data from the source.

The output of the data source is converted from serial form at 2000 bits per second to parallel form at 1000 bits per second in converterlll. The converter may be of any conventional form such as a two-stage shift register. It furnishes outputs on lines A `'and B corresponding to the iiist and second data bit of each Ldibit pair. The input between dibit intervals on line `18 from delay net- Work 17 resets the converter.

`Outputs A and B are sampled at the appropriate time by vector keyer i12 under the timing control of the output of clock generator 16. Keyer 12v is a novel three-stage binary counting register las more fully described below. Its countdown rate is controlled by the output of clock 1r-6.

The countdown is modiied `arithmetical-ly in accordance with the signal combination -found on leads A and B to produce three simultaneous outputs on leads marked 45, and 180 degrees. The sum of these outputs at any time determines the phase of the Vcarrier wave in modula-l l 'generator- 15 to square waves at four, two and `one times the carrierfrequencyf The v45, 9,0'- andl lSO-degree outthat properly phased rectangular waves .are produced at 'y the carrier frequency as an output signal. The four times carrier vfrequency square wave provides eight transitions corresponding to LlS-degree increments at the carrier frequency. The two times carrier frequency square wave similarly provides four transitions corresponding to 90- degree increments at the carrier irequency. Finally the carrier frequency `square wave provides two transitions cor-responding to ISU-degree positions of thecarrier frequency.. Thus, alternate gatin-gof the carrier frequency* square wave to the output bistable circuit produces an output rectangular wave at the carrier frequency. Simultaneous gating of the proper transitions of the four and two times carrier frequency square waves to the bistable output `circuit determines the proper phase. The manner in -whichthe gating is controlled by the vector keyer is l more fullydescribed below.

Filter 14 is -a low-passfilterfof any. conventional type v with a cutoff frequency above the, desired carrierA frequency andbelow thethird harmonic thereof. Av convenient cutoff point may be at 3G00 cycles per secon-d, the upper limit ofthe frequency pass-band oflmost voice circuits.. This cutoif frequency will aid in producing Vaproper match to the transmission Iline and will result inlan output of sine form. n l i The system of FIG. l'isexplained' in more'detail in connection with the description of FIGS. 3 through-6.

FIG. 2 is diagrammatic of lanother embodiment of this invention in which the carrier Wave is sinusoidal throughout. A complete .tna'nsmitter according to FIG. 2Y includes all apparatus shown in FIG. l to the left of the vertical dot-dash une A A. "nre 45.90. und 18o-de4 grec outputs of the vector keyer 12 in FIG. 1 are applied to separate modulators in FIG.2. r

The new apparatus in the embodiment of FIG; 2 in'- `cludes a sinusoidal carrier wave generator 2i), which may be-any conventionaltype. Acrystal-controlled oscillator is suggested. The frequencyis assumed to be 150() cycles per second. The output'fof generator 20 is split into two paths. Onepath to the left in FIG. 2 is connected directly to phase-reversing modulatorV 21. The other path includes a 90-degreeV passive phase-shiftingcircuit '22V of any well-known kind.V i 'Ihe outputf of the `phase-shifter 22 isy applied to a second modulator 23,

which is yidentical to modulator 21. The outputs of both 5 l com-mon output, such as two triodes having lacomm'on plate circuit and separate Igrid circuits.

The summer output is further adjusted by degrees or not in` phase-shifter 25 according to whether a signal is presenten or absent from the 45-degree lead from the vector keyer 12 in FIG. l. 'I'he signal from the keyer may be arranged to insert or'rem'ove the phase-shifter from the outgoing path to theline. The phase-shifter `output is the line signal and during any dibit interval may belany one of the eightphases 4indicated on vector diagram 27.

The vector lkeyer yof FIG. l is seen, therefore, tobe adaptable to producing .a phase-shifted carrier signal solely by digital means vas in FIG. 1 or by means `of 'reversing-type modu-liatorslas in FIG. 2. FIGS. 3, 4"andf5 taken together fill out the details of the all-,digital system according to FIG. l. FIG. 6 is a .pulse diagram showing the waveforms occurring at different points inthe circuits of these figures for a typical random data message. Y p

. FIG. 3 is a diagrammatic of a practical serial-to-parallel converter for performing the function of block 11 of FIG. v

il. Two ilip-op registers` 32. and 33 rstore successive serialfl pulses under control of clock generator .16. Registers. 32";and' 33:.are represented as having two inputs designated set S and reset R, and two outputs designated l and 0. These registers iare conventionalbistable circuits employing electron tubes or transistors and function in a Well-known manner. The outputs of the two registers are also designated A, A', B and B'. There is an output Aon A or B when the l output is grounded.

At this time the primed outputs are at a negative polarity. 'Convensely, when the 0 outputs are at lground there is ia usefuloutput on A and B' `and negative voltage on A `and B.

Clock generator 16 produces a square Waveioutput at the dibit rate or 100G-cycles per second. This is diagramrned on line (a) of FIG. 6 and is labeled BS. The other output (BS) is the inverse or complement of this square wave. The outputs BS and (BS) 'are delayed in network 17l to produce square wave BSD (shown ion line (c) of FIG. v6) and its complement (BSD).` The BSD and (BSD) square waves alternately enable and disable coinmodulators are combined in a summer, or adding, circuit 24.*V From thefsummer the combined output is applied through a passive 45-degree phase-:shifter-to the output line. v

the lSO-degreelead. from the vector keyer12 in FIG. li

Modulator'Zl is controlled or'reversed by the signalon The input to this modulator is represented on the figure as the reference phase. Tfhe'out-put may be eithergthe reference phase or its opposite ISO-degree phase. VMod-u- 'latorf 21 is, therefore, equivalent in operation to a doublepole double-throw switch and may` include an inputand output transformer interconnected by a rectiiier bridgey biased by the lSO-degree signal. u Y

Modulator 23 yis identical to-modulator 21, except that it receives a 90d'egree carrier phase from the phase'- shifter-*22 and isy controlled bythe 49Odegree output of vector keyer12rin'FIG. l. 'Its output may be either the 90- or 27U-degree phase indicated.

The outputs of modulators 21' and 23 lare combined in summer 24 to `produce a resultant phase that maybe any one of the quadrature phases indicated onvector diagram 26, namely: "45, `135, 225, or 315 degrees laccording to the control signals on leads 9()l and l80"degrees from' the vectorl keyer 12 in FIG. l. The summer may be any common combining circuit having, separate inputs and a cidence gates 30 and 31 indicatedconventionally by half circles. rIlhe output of serial data source 10 is applied vto'ggates 30 and 31 inparallel. The outputs of the gates connect to the set inputs of lthe respective registers 32 and 33'.

A typical data message is shown on line (e)"ofFIG.

6 as the sequence 001011010001101l. Lines (f) and (g) of FIG'.'6 show the resulting condi-tion of the registers 32 and 33 for this sequence ot'` data. Just prior to the start 'cfa new BSD squarewave a reset pulse (shown-in iine (d) yof'FIG. 6) is delivered tothe R inputs of registers 32 and 33, as shown, to restore them to their normal condition-"-ground jon the primed outputs.V l"Registers 32 and 23 are filled and :emptied in an obvious manner.

FIG. `4 shows the vector keyer 12 vof FIG. las compn'sing three tlipeilop or memory cincuits 41, 45 and 53 connected in tandem through appropriate coincidence (commonly called AND) and isolating (commonly called OR) igates. vIhe'leftehand ilip-op 41 is driven by the BS square wave FIG. 3 through a differentiating capacitor 40. Thiswave is shown on line '(b) of FIG. 6. The S and R inputs of nip-flop 41 ane connectedinparallel so Itihat'it is' alternately set and reset by the BS pulse for a countdown of two. The output of flip-dop 41vappears as the;45-degree output and its complement yof the vector keyer and is unalected by the condition lof the registers Aand B in FIG. 3. Line (h) of FIG. 6 Ishows this output.

The outputs of lifip-flop41 are connected to the inputs flipflop 46 through coincidence gates 42 or 43, isolatinggatelit4 coincidence lgate 45. Gates 42 and 4-3 jare enabled in thev alternative by thev condition-of the B register of FIG. 3. Flip-liep 46 is, therefore, set or f-nom the-BS input'by four in nonmal ascending numerical order: i.e'., 0, 1, 2, 3, 4. However, with a 1 signal in the B register, hip-flop 4 6 is controlled by the complementary output of dip-flop 41 in the manner ofa binary subtnactor in descending numerical order: ie., 4, 3, '2, 1, 0. 'IThe output of flip-llop 46 appears as in Line (i) of FIG. 6 for the representative B register conditions shown on line (g) of FIG. 6.

Flip-dop 53 is identical to flip-ops 41 yand 46, except that it isdriven by the output of either iiipdlop 46 vor 41 depending on the condition of the A and B signal registers. Coincidence lgates 49 and 50 are enabled or not in accordance with the condition of the A register. Since the-inputsto flip-flops 46 and '53 are controlled through coincidence :gates 45 and 52 which are enabled by the BS pulse on line 54, the nip-flops operate not on the 'transitions in the preceding Hip-tiops but on the condition thereof just prior to the occurrence of the BS pulse. It is assumed "that there is an inherent delay in the change of state in each flip-nop after the application of the driving pulses. To avoid untimely reopenations of the flip-flop Y513 when the preceding flip-.flop `46 does not change its 45 degrees to the previ-ous carrier phase, 'and the code 11 Ysubtracts 45 degrees therefnom. Similarly, .the code (l1 Vadds 135 degrees to the previous phase and the code 10 subtracts 135 degrees. Truth or logic tables of codes may be [made up to illustnate the operation of the keyer circuit. Dinect outputs are designated "1 and ab- I sence of an output by 0.f Achange of 1 in the least lsignn'cant `digit is equivalent to a phase shift of 45 degrees. Similarly'. changes of '1 in the next bigher digits to prepare'to change state to 11 gate 44 over lead 55 partially enables gates 49 and 50'. Thefl .standing on lead A [fully enables gate 49. -I-Iowever, iiip-flop 46 lhad no output and no change onderis sent to ilip-llop 5131. The yunalV state of the ilip-op is there- .fore 0110, representing a total phase shift of 90-45=45 degrees advance.

rIlhe change in lip-ilop states from 111 in the fourth dibit interval in FIG. 6 for the code signal combination 11 to `110, i.e., subtraction of one, can be traced in a similar fashion using the last three columns of Table I and remembering vthat gates 43 and 5t) are enabled by the A and B outputs bt the signal registers nather than gates 42 and 49.

Por the unlike codes 01 and 10 which require 135- degree phase shifts equivalent to the addition or subtraction of a binary 3, the loop feeding the output of flip-flop 41 directly to flip-Hop 53 comes into use. Consider the change in the third dibit interval in FIG. 6 for the code 10. The ip-ops ended the previous interval in the 010 state las previously developed. Table I re-l quires a change to the condition 111. The BS pulse at the beginning of thel thind interval changes the state of flip-flop 41 as before. The signal on the B lead enables gate 42. Since, however, flip-flop 41 had no 1 output just prior to the occurrence of the BS pulse,"n0 y change occurs in flip-flop 46.. Further, itis seen that no.

` enabling :output on lead 55 is communicated to gates 49 lare' equivalent to phase shifts of 90 and 180 degrees,

mreotivel'y- T trible I pCode o3 V01 1o. n 11 Add l Add 136 Subtract 135 Subtract 45' 180 -90 45ok 1809,90? 45 y1809,90o v45" 180 90 45- o 00.0. oroy o ou o o 0-o. o o v1 o 1 1 1 o` 1 1 r- 1 0 `1 0 l 1 1 0 0' 1 V0 1 14 0 f 0 1 1 o 0 1 1 1 1 1 1 o 1 1 0 0v 1 0 O 1 0 0 1 0 Y 0 1 0 1 1 1 Y 1 0 l 0 1 1' (lv l 1 1 `1 .0 0 1 0 1 1 0 Y 0y 1 0 1 1 1 1 o 1 o 1 1 Y' o o 1 The operation of the vector keyer of` 4 can be and 50 at the output yof flipdlop` 46, and no change order is delivered to flip-flop 53 from flip-flop 46. The AB (10) code has, however, enabled gate 47, which is also connected to the 0 output of nip-flop 41, then activated. Therefore, a 1 is delivered through coincidence gate 47, isolating gate 51 andcoincidence gate 52 t-o flip-,ilop`53 which changes its state. The linal condition is lll as required by Table I, an advance 'of 180+45=225 degrees equivalent to a retardation in phase of 135 degrees.

The operation of the vector keyer ofr FIG. 4v for the signal code 01V is similar to that for signal code 10 ex? cept that coincidence gate 48 is enabled instead of gate 47. For the circuit conditions of the fth dibit interval, however, it may be noted that although gate 48 is enabled -by the signal register there is no output on the 45-degreelead of-ilip-flop 41. Flip-flopvSS neverthelessVV is caused to change its `state by way of ygate 49 which is enabled on signal leadA, lead 55 and the 90- degree output of flip-flop 46. rIlhe condition'of the fliptlops, therefore, changes from 110 vto 001 as required byV Table I. Y

FIG. 5 illustrates a modulator for digital phase-shifted` carrier generation. The square-Wave generator 15 cornshown; t0 be that of :a three-digit binary computer with.,

the aid of Table I and FIG. 6. Assurnefthat the flipaflops 41,' 46v land '53 are in the states;k indicated in the lirst dibit interval of FIG. `6 with the 00 code standing in the signal registers, namely: 001. The Q01-code lfrom Table I requires a phase shift of 45 degrees, Le., addition of one, tothe condition 010. Upon the occurrence of the BS pulse the flip-flop 441 preparesto change its state to 0 regardless of thefcode. B lis (l Awithv the result that coin;

, prises'a sinusoidal generator 60 which operates at eight' times the carrier frequency of 1500 cycles per second orV 12 kilocycles per second. It may be orystalfcontrolled, if desired. 'Ihe output lof sinusoidal oscillator 60 'is passed through a squarer 61, which changes the sinewave output of |oscillator 60 into a rectangular wave at the same frequency. FDhe modulator proper comprises a three-stage binary counter 62., 6-3 and 64, a rst group of coincidence gates 65 through 72, a group of isolating gates 73 through 76, a second group of coincidence gates 77 and 78, an -output filip-flop 79V and -a low-pass iilter 14. The binary counters 62, 63 and l64 operate as countdown or frequency-dividing circuits and have respectively outputs of tour times, two times andl one times the carrier frequency. The counters are conventional Hip-flop cidence gate 42 is enabled.V VSince flip-flop Y41 `at this inn circuits, each succeeding one being driven by the 0 output Ioli the preceding. The outputs of the counters are used to operate the output flip-ii'op circuit 79 through the several gates under the contnol of the outputs 'from the vector keyerof FIG. 4. The outputs of the generator 15 and counters 62, 63 1and'64 are shown in FIG. 6 on lines-( k), (l),(m') :and (n), respectively.

To illustrate theV operation of the modulator of FIG. 5 assume that the outputs from the vector keyer are as The'l in the output of therefore operates through isolating gate 73 to set iipflop 79 whenever counters 62, r63. and 64 have simultaneous 1, and 0'outputs, respectively.V Similarly, flip flop79is reset through gate 'I8 whenever the counters have respectively 1, 0 and lloutputs. Thus, flipdop '79 produces arectangular waveoutput at. carrier rate determined bycounter .64 withphase synchronized with the Outputs of counters 62k and 63. Fllhe gating operations -for other vector keyer output combinations can be traced in a. similar fashion. The vector keyer of FIG. 4 is seen to serve las a memory of Uhevphase being transmitted.

Line (o) of FIG. l6 shows the resultantV phase-shifted rectangular waves for the message previously assumed. The phase shifts in each dibit interval with respect to the previous dibit interval are marked lon FIG. 6. The absolutev phase is also shown vfor comparison. The dotted square waves are continuations Vof those in the previous interval for the purpose of showing the 'phase shift graphically. The absolute phases show that the phase changes between signals shift from one quadrature set of phases which are odd multiplesl of 45 degrees to .am

said single frequency, `a source of timing pulses synchronized `with said master source and representing a transmission rate for said pairsk of binary signals lower than said single frequency, frequency dividing means driven by said master source for-deriving said single frequency and multiples thereof, a source of data signals occurring at twice said transmission rate, means fortranslating serial data-signals from said data source to parallel form in pairs, a transmission line, and logic circuitry for key- :ing said -`frequency dividing means to said transmission line at intervals phase-shifted in response to said timing Lpulses andM to said translated'data signals'by a multiple other setv of phases which are even multiples of 4 5 de-v grees as previously mentioned V `It is Vapparent from the above description that only the square waves four, twol'andone times'the carrier :fre quency 'are needed in the modulator of "FIG. 5.]Amaster oscillator at eight times the carrier .frequency is shown `however, `for a practicalreason.V When converting a Isineble to slice the sine-wave atl precisely the '.zero. level. Rather slicing yoccurs above or'ibelow'the zero level.

symmetrical in its positive and negative half-cycles.` But rfor the purpose of defining accurateZtS-degree intervals in thecarrier wave, .la symmetrical ysquareiwave latfour transitioninthe eight times carrier :frequency-wave oc- Vcursat. theA proper instant and only these transitions are usedto control the frequency division to the four times icarrierfreq'uency square Wave. v AIf an ideal squarefwave at four times the carrier frequency isravailable, no higher harmonic is needed. f

"Line (p) of FIG. 6 shows the appearance of the line signal obtained by passing the square wave signal Of line (o) through a low-pass lter 14 indicated in FIG. 5.

v In a receiver for such a signal a detector for comparing the vfull one-and-a-half cycles ofrsuccessive dibit intervals is required.

The output of the specific vector keyer .of FIG. 5 can also be used to controla sinusoidal wave as indicated `in FIG. 2 in the manner already indicated. I

Whilethis invention has been described by means of specific embodiments, vit isnot intended to be limited to these examples. Equivalent embodiments may be conceived by those skilled in the art.V |T he counters and flipv flopsmay comprise electron tubes of transistors. Diodes or transistors may be use d'inv the. g ate circuits. Other'k ratios between message and carrier rates may also be employed. "This inventionhasapplicationfto a phasernodulation transmission system Vsuch as is disclosed in the application of 139A. Baker, Serial No: 49,544, led

times the carrier frequencyis essentiah Every 'other f wave into a square wave, it is not often practically feasi- AThis tends 'to make the resultant rectangular Wave unof 45 degrees in accordance with the` relationship between successive pairs of data signals whereby a predetermined shift in the phase of said single frequency occurs for every-successive pair of data signals.

2. A transmitter for a communication system in which pairs of successive binary digital signals are encoded on a phase-shifted carrier wave of a single frequency as one v of eight preselected lrelative phases comprisingfa serial data source, means for lconverting the output of said data source into two-bit'parallel form, a clock` generator for synchronizing the `operations of said transmitter and for determining the interval of time during which each successive digit pair is transmitted, rde'cisionaldogic means underlvthe control of said clock generator for sampling the` output of said converterr and for computing the amount of phase shift necessary to transmit each particular `digit pair according to a predetermined code, a master oscillator for generating a wave in fixed' relation with the frequency of said carrier wave, modulator means responsive to the outputof said logic means for imparting to thel output of said masteroscillator the phase shift determined by said logic means.

3. A transmitter according to claim 2 in which vthe .output of said master oscillator is a'square wave atleast four times the frequency of said carrier wave, said logic means is a three-stage binaryrcounter, and said modulator is a three-stage frequency divider.

.4L\ A transmitter according to claim 2 in l'whichvthe output ofV said master oscillator Vis a sine-wave at said carrier frequency, and said modulator comprisesa firstl switching device for reversing theV phase of thedirect output of the master oscillator under the control of one output of said logic means, a quadrature phase-shifter for the output of the master oscillator, a second switching device for reversing thel phase of the output of said phase-shifter under'the control of a second output of said logic means, a mixer 'circuit lfor combining the output of said first rand second switching devices, and a 45-'degree phase-shifter coupled to .the output of said mixer circuit and inserted or not under the control of a third output of said logic means.

- V5. In a phase-modulated carrier transmissionsystem in which said `carrier may be any one of eight preselected relative phases, a transmitter comprising a source of serial binary d ata message, signals, means for translating sai-d serial data signals into different onesof `four dibit pair combinations at a .synchronous rate, a clock source for controlling said synchronousrate, a stable frequency source having a frequency atleast four times that of said carrier wave, means for converting the output of said frequency source into square waves, means for frequency dividing the output of said converting means into square lator to the input of said output bistable circuit in a 'sequence to form said phase-shifted 'carrier Wave.-

6. A phase-pulse generator for modulating a single frequency with simultaneous intormation from a pair of vbinary data channels comprising two sources of binary data, a source of timing pulses for synchronizing said dat-a sources, a source of rectangular Waves lat eight times said single frequency, means for encoding the simultaneous outputs of nsaid data sources as predetermined incremental phase shifts of a multiple of 45 electrical degrees in three- Vdigit binary forms, means for frequency dividing the outu put of -said rectangular wave source into further recn relative phase shifts of an integral multiple of 45 electrical degrees comprising la serial datasource, means for pairing Vdata bits emitted from said data source, a source of tun.-

ing pulses occurring at half the seri-al data rate, a stable i source of electrical oscillations, means under the control of said timing source for computing .from the paired combinations standing in said pai-ring means in cach timing interval the corresponding amount of phase shift as a three-digit binary number according to a predetermined code, said three-digit number representingphase shifts of 45, 90 and 180 electrical degrees in order of increasin-g digit significance, an output =circuit, and means for modulating the output of said computing means with lthe output of said source of oscillations to form in Said output circuit a coded sequential phase-shifted wave Iof said single frequency. v

8. The generator according to claim 7 in which said stable source of oscillations. produces a rectangular wave at eight times said single frequency, said computing means comprises three bistable circuits each having two stages, v

a common input point and complementary output points, the first of said circuits being complemented by each timing pulse, a first pair of coincidence gates coupled to the respectivel outputs of said rst bistable circuit and enabled in the -alternative according las the' second signal element of a data bit pair is present or absent, a first isolating gate interconnecting the outputs of said first coincidence gates andthe input point of the second bistable circuit whereby the output of the latter is complemented or not by the concurrence or not of inputs to either of said iirstfcoincidence gates, Ya second pair of coincidence t gates coupled to the respective outputs of said second bistable circuit and enabled in the yalternative according as the first signal element of a data bit pair is present or absent, a third pair of coincidence gates coupled to the respective outputs `of saidrst bistable circuit l.and enabled 'f in the alternative according to the order in'which the first and second signal elements are simultaneously unlike and an output appears concurrently-on the corresponding output Vof said rst bistablecircuit, a second isolating gate Vinterconnecting the output of said second and third pairs p of coincidence gates to the input point of the third bistable circuit whereby said third bistable circuit is complemented by the outputs of said first andsecondbistable circuits dior certain signal combinations, and further coincidence gates n shifts to be imparted to said single frequency for each` respectively controlling the connections of said first and second isolating gates to the input points of ysaid second and thirdl bistable circuits onlywhen said clock pulse occurs, and said modulator means comprisesl three bistable circuits each having an input point and complementary spectively, a rst pair of coincidenceY gates connected to the complementary outputs of said first =bistablecircuit and enabled in the alternative -by the complementary outputs of the first bistable circuit of said computing means, a second pair of coincidence gates connected to the complementary outputs of said second bistable circuit and enabled Vi-n the alternative by the complementary outputs 'of the second bistable circuit of said computing means, a

y group of four coincidence gates connected in 4pains to the complementary outputs of said third bistable circuit and one in each of said pairs enable-d in the alternative by the complementary outputs of the third bistable circuit of said computing means, a group of four isolating gates for combining the outputs of said first pair, said second pair, and the separate pairs of said group of four coincidence gates respectively, an output bistable circuit having set `and reset input points yand an output point, a pair of threeinput coincidence gates having output points connected v respectively to the set and reset input points of said'output bistable circuit and enabled simultaneous-ly by the outputs of the first and second of said last-mentioned isolating gates and alternatively by the outputs of the-third land fourth of sai-d last-mentioned isolating gates.

9. A transmitter for encoding serial binary data taken two at a time into relative phase shifts of a single carrier frequency comprising a source of serial data, means for converting the output -of said data source into dibit combinations at a synchronous rate, there being four such dibit combinations, a clock source for determining said synchronous rate, means under the joint control of said clock source and said converting means for computing according to a preselected code successive phase successivedibit combination in the form of a three-digit binary number corresponding respectively to phase shifts of 45, andj1 80 degrees in increasing order of digit significance, a master source of stable'oscillations, means for frequency dividing the output of said master source into rectangular waves fourptwo andone times said single frequency, a bistable output circuit having set and reset input points, and means responsive to the 45-, 90- and 180- degree digits of said computing means' for sequentially gating the four, two and one times outputs, respectively, of said frequency dividing means to the input points of said output circuit toY form said phase-shifted single-frequency output signal. 10. A transmitter for encoding serial binary data take two at a time into relative phase shifts of a single fre- Y quency carrier Wave comprisinga source of serial data,

means for converting the output of said data source :into

dibit combinations at a synchronous rate, a clock source gated to said converting means for determining said synchronous rate, means for computing according to a preselected code successive phase shifts to be imparted'to said single frequency carrier Iwave for each successive dibit combination in the form of a' three. digit binary number corresponding respectively to phase shifts ofv 45, 90 and 18() degrees in increasing order of digit significance, the outputs of said computing means being on-olf -signals correspondingto the presence or absence of each of said 45-, 90'- and ISO-degree phase shifts, a stable source of said vsingle frequency, a first modulator connected directly to the output of said stable source controlled by the ISO-degree output of said computing means for reversing the phase of the output of said stable source or not according` to the presence or absence of said 180'- degree output, a quadrature phase-shifter connected to the output of said stable source, a second modulator connected to the output of said phase-shifter controlled by the 90-degree output ofsaid computing means for reversing the output of said phase-shifter or not according to the presence or absence of saidv 90degree output, a sum- 13 ming circuit for combining the outputs of said rst and second modulators to form an output at said single frequency in one or four quadrature phases, a 45-degree phase-shifter, and means for switching said 45-degree phase-shifter in series with the output of said summing 5 circuit or not according to the presence or absence of said L15-deg1fee output to form a line signal at said single References Cited in the le of this patent UNITED STATES PATENTS Bliss Nov. 5, 1940 Harris June 7, 195'5 

2. A TRANSMITTER FOR A COMMUNICATION SYSTEM IN WHICH PAIRS OF SUCCESSIVE BINARY DIGITAL SIGNALS ARE ENCODED ON A PHASE-SHIFTED CARRIER WAVE OF A SINGLE FREQUENCY AS ONE OF EIGHT PRESELECTED RELATIVE PHASES COMPRISING A SERIAL DATA SOURCE, MEANS FOR CONVERTING THE OUTPUT OF SAID DATA SOURCE INTO TWO-BIT PARALLEL FORM, A CLOCK GENERATOR FOR SYNCHRONIZING THE OPERATIONS OF SAID TRANSMITTER AND FOR DETERMINING THE INTERVAL OF TIME DURING WHICH EACH SUCCESSIVE DIGIT PAIR IS TRANSMITTED, DECISIONAL LOGIC MEANS UNDER THE CONTROL OF SAID CLOCK GENERATOR FOR SAMPLING THE OUTPUT OF SAID CONVERTER AND FOR COMPUTING THE AMOUNT OF PHASE SHIFT NECESSARY TO TRANSMIT EACH PARTICULAR DIGIT PAIR ACCORDING TO A PREDETERMINED CODE, A MASTER OSCILLATOR FOR GENERATING A WAVE IN FIXED RELATION WITH THE FREQUENCY OF SAID CARRIER WAVE, MODULATOR MEANS RESPONSIVE TO THE OUTPUT OF SAID LOGIC MEANS FOR IMPARTING TO THE OUTPUT OF SAID MASTER OSCILLATOR THE PHASE SHIFT DETERMINED BY SAID LOGIC MEANS. 